A new family of semidynamic and dynamic flip-flops with embedded logic forhigh-performance processors

In an attempt to reduce the pipeline overhead, a new family of edge-trigger ed flip-flops has been developed. The hip-hops belong to a class of semidyn amic and dynamic circuits that can interface to both static and dynamic cir cuits. The main features of the basic design are short latency, small clock load, small area, and a single-phase clock scheme, Furthermore, the hip-ho p family has the capability of easily incorporating logic functions with a small delay penalty, This feature greatly; reduces the pipeline overhead, s ince each hip-hop can be viewed as a special logic gate that serves as a sy nchronization element as well. The flip-flop family presented in this paper has played an integral role in meeting the cycle-time goal of the micropro cessor reported in [1].