A new lateral power MOSFET for smart power ICs: the "LUDMOS concept"

In this paper, a new concept of lateral DMOSFET for medium voltage (<100 V) smart power integrated circuits is proposed. These structures present a tr ench in the drift region filled with oxide or with oxide and polysilicon. T hese structures called LUDMOSFET feature a reduced specific on-resistance a nd enhanced breakdown voltage. Far example, for a breakdown voltage of 50 V , the specific on-resistance is 1.2 m Omega cm(2) in the conventional LDMOS FET, 0.8 m Omega cm(2) in the LUDMOS without polysilicon (i.e. 30 percent r eduction) and 0.6 m Omega cm(2) in the LUDMOS with polysilicon (i.e. 50 per cent reduction). They are technologically compatible with advanced CMOS pro cesses using trench isolation. (C) 1999 Elsevier Science Ltd, All rights re served.