A VLSI design for implementation of transform domain adaptive filters

A VLSI implementation of a dedicated digital signal processor is presented. The processor is tailored for efficient implementation of transform domain adaptive filters. It incorporates a butterfly processor which performs but terfly operation to implement the required transformation. It is also able to perform complex addition, subtraction and multiplication. The butterfly processor makes use of a redundant binary tree multiplier with a recently p roposed coding of signed-digit numbers which reduces the number of levels i n the tree by one. An on-chip read only memory holds the transformation coe fficients. The contents of the ROM determine the type of transform. The pro cessor incorporates an ALU to perform integer arithmetic, address calculati ons and implementation of circular memory scheme. For fastest accessibility , the essential variables of the algorithm are implemented in a register fi re.