System-level time-stationary control synthesis for pipelined data paths

We address the problem of time-stationary control synthesis for pipelined d ata paths. Control synthesis system accepts scheduled control data flow gra ph with conditional branches which are produced by high level synthesis too ls such as Sehwa [1] as input specification and generates a FSM controller. First a scheduled control/data flow graph is analyzed and the various stat es are identified. Overlapped states are grouped together to produce L grou ps where L is the pipeline latency. Next, state transitions are identified and a state table is generated. Finally, a highly optimized FSM controller is implemented by performing horizontal partitioning and the corresponding stae encoding so as to minimize the total controller area. We compared our approach to published work on FSM generation and optimization and the resul ts indicate that our method results in large savings in total controller ar ea.