Abstract architecture representation using VSPEC

Complex digital systems are often decomposed into architectures very early in the design process. Unfortunately, traditional simulation based language s such as VHDL do not allow the impact of these architectural decisions to be evaluated until a complete, simulatable design of the system is availabl e. After a complete design is available, architectural errors an time-consu ming and expensive to correct. However, there is an alternative to simulati on based techniques: formal analysis of abstract architectures at the requi rements level, This paper describes VSPEC's approach for defining and analy zing abstract architectures. VSPEC is a Larch interface language for VHDL t hat allows a designer to specify the requirements of a VHDL entity using th e canonical Larch approach. VHDL structural architectures that instantiate VSPEC entities define abstract architectures. These abstract architectures can be evaluated at the requirements level to determine the impact of archi tectural decisions. This paper briefly introduces VSPEC, provides a formal definition of VSPEC abstract architectures and presents two examples that i llustrate the architectural definition capabilities of the language.