Analog-to-digital converter survey and analysis

Authors
Citation
Rh. Walden, Analog-to-digital converter survey and analysis, IEEE J SEL, 17(4), 1999, pp. 539-550
Citations number
33
Categorie Soggetti
Information Tecnology & Communication Systems
Journal title
IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS
ISSN journal
07338716 → ACNP
Volume
17
Issue
4
Year of publication
1999
Pages
539 - 550
Database
ISI
SICI code
0733-8716(199904)17:4<539:ACSAA>2.0.ZU;2-U
Abstract
Analog-to-digital converters (ADC's) are ubiquitous, critical components of software radio and other signal processing systems. This paper surveys the state-of-the-art of ADC's, including experimental converters and commercia lly available parts, The distribution of resolution versus sampling rate pr ovides insight into ADC performance limitations, At sampling rates below 2 million samples per second (Ms/s), resolution appears to be limited by ther mal noise. At sampling rates ranging from similar to 2 Ms/s to similar to 4 giga samples per second (Gs/s), resolution falls off by similar to 1 bit f or every doubling of the sampling rate. This behavior may be attributed to uncertainty in the sampling instant due to aperture jitter. For ADC's opera ting at multi-Gs/s rates, the speed of the device technology is also a limi ting factor due to comparator ambiguity. Many ADC architectures and integra ted circuit technologies have been proposed and implemented to push back th ese limits. The recent trend toward single-chip ADC's brings tower power di ssipation, However, technological progress as measured by the product of th e ADC resolution (bits) times the sampling rate is slow. Average improvemen t is only similar to 1.5 bits for any given sampling frequency over the las t six-eight years.