This paper proposes a method to avoid current feedback filters in fast digi
tal-based current loops in switched reluctance drives. Symmetrical pulsewid
th modulation (PWM) and synchronized sampling of the phase current allow a
noise-free current sampling with no antialiasing filter. This paper also pr
oposes more efficient methods to chop the two transistors in the asymmetric
inverter used with switched reluctance drives. A fast field-programmable g
ate array (FPGA)-based test system is used for validation of the new method
s. Test results show a significant improvement in dynamic and steady-state
current loop control compared with traditional methods. The new chopping me
thod is found to reduce the switching losses and increase the drive efficie
ncy.