LATENCY-FREE AND HAZARD-FREE VOLUME MEMORY ARCHITECTURE FOR DIRECT VOLUME RENDERING

Real-time direct volume rendering (ray-casting or volume ray-tracing) is achieved by problem specific rendering architectures. The performan ce of these architectures is however limited by the access to the volu me memory. Although many different volume memory architectures have be en proposed and realized, none of them uses the read-out-gain provided by new DRAM interfaces like Rambus-DRAM, SDRAM etc. In this paper a s olution is presented that allows profit from these new interfaces. The key feature of the new architecture is a multi-level cache system wit h software prefetching and latency hiding. By allowing the rendering p ipeline processor to operate at up to 200 MHz, a 512(3) data set store d in a single memory module can be rendered at 3.125 Hz. An even highe r performance is possible from the DRAM side but is limited by current SRAM and processor speeds. (C) 1997 Elsevier Science Ltd.