A circuit architecture for analog on-chip back propagation learning with local learning rate adaptation

In this paper we present the analog CMOS architecture of a Multi Layer Perc eptron network with on-chip stochastic Back Propagation learning. The learn ing algorithm is based on a local learning rate adaptation technique which makes the on-chip implementation more efficient (i.e. fast convergence spee d) with respect to similar architectures presented in the literature. Circu it simulation results on the XOR learning problem validate the network beha vior.