Scalability analysis for conservative simulation of logical circuits

We investigate conservative parallel discrete event simulations for logical circuits on shared-memory multiprocessors. For a first estimation of the p ossible speedup, we extend the critical path analysis technique by partitio ning strategies. To incorporate overhead due to the management of data stru ctures, we use a simulation on an ideal parallel machine (PRAM). This simul ation can be directly executed on the SB-PRAM prototype, yielding both an i mplementation and a basis for data structure optimizations. One of the majo r tools to achieve these optimizations is the SB-PRAM's hardware support fo r parallel prefix operations. Our reimplementation of the PTHOR program on the SB-PRAM yields substantially higher speedups than before.