A 2.7 VCMOS analog front end for CCD video systems

A 2.7 V analog front end (AFE) is integrated with a 10-bit ADC for applicat ion in CCD video systems. The AFE consists of a correlated double sampler ( CDS) and a programmable gain (from 6 dB-38 dB) amplifier (PGA). The PGA is implemented by two stages of digitally controlled transconductors. New circ uit techniques are used to implement the AFE in CMOS technology using a 2.7 V supply to handle at least a 0.8 V input signal. The sampling rate of the chip is over 15 MHz. The AFE consumes less than 20 mA. The measured integr al non-linearity (INL) of the chip with the CCD input under 0.7 V is 9 LSB. The differential non-linearity (DNL) is +/- 0.5 LSB.