Input-free V-TP and -V-TN extractor circuits realized on the same chip

The paper describes a self-biased CMOS transistor circuit with two outputs providing the transistor threshold voltages, V-TP and -V-TN. Both outputs a re referenced to the same V-DD supply line, and hence, the circuit can be u sed as a convenient test device. The V-TP extractor is based on the "nested " connection of two transistors; the -V-TN extractor is designed using the difference of gate-source voltages in two different size transistors carryi ng equal currents. The circuit was realized in 0.8 mu m technology, and the results of simulation and experiment are compared. Recommendations to impr ove the design are given.