A single chip 160 Mbit/s cable communication circuit including a gain controlled equalizer and a data regenerating PFLL

In this paper a single chip transmitter and receiver interface circuit for 160 Mbit/s CMI-coded data transmission is presented. The receiver circuit i ncludes a 12 dB cable equalizer to compensate for nonconstant cable attenua tions. There is also a PFLL for data regeneration and to extract a 320 MHz oscillator clock signal. The frequency characteristics of the equalizer are controlled with an automatic gain control loop (AGC). The PFLL is a combin ation of two separate control loops, the purpose of which is to keep the in tegrated oscillator on the narrow locking range of the data loop. The frequ ency loop has been designed with a frequency detector to avoid interference s between the two control loops. The transmitter includes a cable driver su pplying a stable 1 Vpp signal amplitude to the transmission line and also a PLL to extract a 320 MHz clock signal.