A 12-bit 100-ns/bit 1.9-mW CMOS switched-current cyclic A D converter

This paper presents a high speed high-resolution low-power CMOS switched-cu rrent cyclic analog-to-digital converter (ADC), The high performance is att ributed to the use of the following components: 1) a high-performance resid ual amplifier which takes two clock cycles to double a current and 2) an ef ficient cyclic redundant signed-digit algorithm which provides 1.5-bit reso lution without using two matched reference currents. Simulation results sho w that the developed ADC achieves 12-bit resolution and a conversion rate o f 100 ns/bit, where the low-cost MOSIS SCAN20 2-mu m CMOS process and 3.3-V supply voltage are employed. The converter has been fabricated and tested. Experimental results on the test chip are also presented. The test chip ac hieves 12-bit resolution with differential nonlinearity of 0.6 LSB and the integral nonlinearity of 0.5 LSB when operated at a 0.8-Msample/s conversio n rate. The power consumption is 1.9 mW.