In this paper, we propose a cost-effective test-generation technique for li
near time-invariant analog circuits subject to the parametric faults. This
technique requires only a small number of test patterns, as opposed to trad
itional functional testing which utilizes complex stimuli, to classify the
circuits. We formulate the test-generation problem as a problem of deriving
hyperplanes in the multidimensional space formed by a set of parameters of
the del ice under test (DUT), These hyperplanes define the acceptance regi
on in the measurement space and can he derived by a search-based heuristic.
The coefficients of the hyperplanes are then used as test patterns for cla
ssification (to determine whether the DUT is in the acceptance region or no
t). A more general case of using arbitrary "linearly independent" test sequ
ence for classification is also discussed. Experimental results show that l
ess than 10% of misclassification can be achieved by a very small number of
tests.