This paper presents a navel recursive algorithm for generating higher order
m-dimensional (m-D) convolution by combining the computation of 3(m) ident
ical lower order (smaller size) convolution computations, and its implement
ation in parallel VLSI networks. The resulting VLSI architectures have very
simple modular structure, highly regular topology, and use simple arithmet
ic units. Additionally, the proposed architectures have very smell depth an
d contain only a single stage of multipliers, while all other stages contai
n adders only.