High throughput VLSI implementation of discrete orthogonal transforms using bit-level vector-matrix multiplier

In this paper, we propose a fully pipelined two-dimensional (2-D) bit-level systolic architecture for efficient implementation of discrete orthogonal transforms using a serial-parallel vector-matrix multiplication scheme base d on the Baugh-Wooley algorithm. Apart from its regularity and simplicity, the proposed structure yields high throughput due to massive parallelism ac ross the 2-D mesh. The area- and time-complexities of the proposed structur e are (ON2) and O(2nN(2)), respectively, for implementation of N-point tran sform, where n is the wordlength.