Performance enhancement of multistage interconnection networks with unit step buffering

Multistage interconnection network (MIN) has been widely used for parallel computer systems, and also recognized as an efficient switching fabric for digital communication. In this paper, we propose a new switching mechanism for MIN's called unit step buffering (USB) which significantly improves the network performance. Here each cell is allowed to move only one buffer ent ry position using short network cycle. The proposed USE scheme is compared to the traditional scheme by analytical modeling and computer simulation, T hey reveal that throughput and delay are improved about 60%-80% for practic al size MIN's with reasonable traffic in asynchronous transfer mode (ATM) s witching environment, Improvement on parallel computer systems with larger size packets is more significant as about 100%, More importantly, the schem e does not require any additional hardware or operational overhead.