Combining multiple DFT schemes with test generation

To reduce total chip production costs, circuits must be more testable. Seve ral design for testability schemes which tradeoff various design parameters have been proposed toward that end. The recently proposed partial reset (P R) method is incorporated. Rather than allowing all memory elements in a se quential circuit to be reset by a primary input, only a subset of them is g iven the capability to reset. PR has less hardware overhead and typically s maller test application times than scan design. PR, furthermore, allows unr estricted at-speed testing. The tradeoff is in slightly lower testability. A dynamic PR flipflop selection method is described utilizing a fast sequen tial test generator. The automated system developed in this research works closely with the test generator to insert PR, observability enhancements an d partial scan into a given circuit. The result is higher fault coverage th an is possible with PR alone and faster test application times than scan de sign. Results are shown on all ISCAS'89 circuits, up to s9234, Even though multiple runs of test generation is performed, CPU times are comparable to a single run of conventional deterministic automatic test pattern generatio ns.