High-level area and power estimation for VLSI circuits

High-level power estimation, when given only a high-level design specificat ion such as a functional or register-transfer level (RTL) description, requ ires high-level estimation of the circuit average activity and total capaci tance. Considering that total capacitance is related to circuit area, this paper addresses the problem of computing the "area complexity" of multioutp ut combinational logic given only their functional description, i.e., Boole an equations, where area complexity refers to the number of gates required for an optimal multilevel implementation of the combinational logic. The pr oposed area model is based on transforming the multioutput Boolean function description into an equivalent single-output function. The area model is e mpirical and results demonstrating its feasibility and utility are presente d. Also, a methodology for converting the gate count estimates, obtained fr om the area model, into capacitance estimates is presented, High-level powe r estimates based on the total capacitance estimates and average activity e stimates are also presented.