Models and algorithms for bounds on leakage in CMOS circuits

Subthreshold leakage current in deep submicron MOS transistors is becoming a significant contributor to power dissipation in CMOS circuits as threshol d voltages and channel lengths are reduced, Consequently, estimation of lea kage current and identification of minimum and maximum leakage conditions a re becoming important, especially in low power applications. In this paper we outline methods for estimating leakage at the circuit level and then pro pose heuristic and exact algorithms to accomplish the same task for random combinational logic. In most cases the heuristic is found to obtain bounds on leakage that are close and often identical to bounds determined by a com plete branch and bound search. Methods are also demonstrated to show how es timation accuracy can be traded off against execution time. The proposed al gorithms have potential application in power management applications or qui escent current (I(D)DQ) testing if one wished to control leakage by applica tion of appropriate input vectors. For a variety of benchmark circuits, lea kage was found to vary by as much as a factor of six over the space of poss ible input vectors.