A cost-effective design for testability: Clock line control and test generation using selective clocking

Clock line control (CLC) is proposed as a new design for testability techni que which can transform a complex test generation problem into many small o nes that are efficiently manageable by selectively enabling or disabling th e synchronous operation of modules. A novel sequential test generation tech nique for the circuits with CLC scheme is also presented. The new test gene ration methodology is able to selectively clock modules, expand multiple ti me frames for a sequential module and compose these local time frames to ge nerate input and clock vectors for an entire circuit. Test generation for t he ISCAS'89 circuits, with and without both CLC has been performed. Higher fault coverage in a shorter time has been achieved using test generation wi th CLC.