High-performance 0.1-mu m gate enhancement-mode InAlAs InGaAs HEMT's usingtwo-step recessed gate technology

Novel approach for making high-performance enhancement-mode InAlAs/InGaAs H EMT's (E-HEMT's) are described for the first time. Most important issue for the fabrication of E-HEMT's is the suppression of the parasitic resistance due to side-etching around the gate periphery during gate recess etching. Two-step recessed gate technology is utilized for this purpose. The first s tep of the gate recess etching removes cap layers wet-chemically down to an InP recess-stopping layer and the second step removes only the recess-stop ping layer by Ar plasma etching. The parasitic component for source resista nce is successfully reduced to less than 0.35 Omega-mm. Etching selectiviti es for both steps are sufficient not to degrade uniformity of devices on th e wafer. The resulting structure achieves a positive threshold voltage of 4 9.0 mV with high transconductance. Due to the etching selectivity, the stan dard deviation of the threshold voltage is as small as 13.3 mV on a 3-in wa fer. A cutoff frequency of 208 GHz is obtained for the 0.1-mu m gate E-HEMT 's. This is therefore one of the promising devices for ultra-high-speed app lications.