Simulation approach for achieving layout independent polysilicon gate etching

Profile and dimension control mechanism in polysilicon gate etching is stud ied systematically by the use of two-dimensional (2-D) etching topography s imulator, Reaction rates are calculated by taking into account interactions between incoming ion/radical fluxes and an ever-changing macroscopic adsor bed particle layer on the film surface. A qualitative guideline is presente d for achieving both anisotropic etched-profile formation and the dimension difference minimization between the inner line pattern width w(i) and the outermost line pattern width w(e) in repeated line and space configuration, When w(e) > w(i) > w(m) (resist mask width), following two possible measur es are necessay, One is to make gas pumping speed large for shortening the residence time of depositive radicals, The other is to make cathode tempera ture high for lowering sticking coefficient of depositive radicals, These a re effective in-reducing the amount of deposited film especially at the Sid ewall of external part of the outermost line pattern (SEP), Higher gas pres sure is also effective in sputtering the deposited film especially at SEP.