The design space of shelving

While using the direct issue mode, dependent instructions cause issue block ages and thus an issue bottleneck. Shelving is a technique to avoid this an d to increase the sustained issue rate. It takes advantage of two concepts: (a) the decoupling of dependency checking from instruction issue and (b) s ignificantly widening the instruction window that is scanned in each clock cycle for executable instructions. In this paper we identify and explore th e design space of shelving. We first outline its main dimensions, then we p resent and discuss feasible design alternatives along three of its crucial dimensions. Finally, we point out which design choices have been made in im portant superscalar processors. For a concise graphical representation of t he design space we make use of DS-trees. (C) 1999 Elsevier Science B.V. All rights reserved.