An accurate performance model of shared buffer ATM switches under hot spottraffic

Asynchronous transfer mode (ATM) switches based on shared buffering are kno wn to have better performance and buffer utilization than input or output q ueued switches. Shared buffer switches do not suffer from head of line bloc king which is a problem in simple input buffering. Shared buffer switches h ave previously been studied under uniform and unbalanced traffic patterns. However, due to the complexity of che model, the performance of such a swit ch, in the presence of a single hot spot, has not been fully explored. In t his article, we develop a model for a multistage ATM switch constructed of shared buffer switching elements and operating under a hot spot traffic pat tern. The model is used to study the switch performance in terms of the thr oughput, cell delay, cell loss probability and the optimal buffer size. (C) 1999 Elsevier Science B.V. All rights reserved.