The design of an SRAM-based field-programmable gate array - Part I: Architecture

Field-programmable gate arrays (FPGA's) are now widely used for the impleme ntation of digital systems, acid many commercial architectures are availabl e. Although the literature and data books contain detailed descriptions of these architectures, there is very little information on how the high-level architecture was chosen, and no information on the circuit-level or physic al design of the devices. This paper describes the high-level architectural design of a static-random-access memory programmable FPGA. A forthcoming P art II will address the circuit design issues through to the physical layou t, The logic block and routing architecture of the FPGA was determined thro ugh experimentation with benchmark circuits and custom-built computer-aided design tools. The resulting logic block is an asymmetric tree of four-inpu t lookup tables that are hard-wired together and a segmented routing archit ecture with a carefully chosen segment length distribution.