Strategy for power-efficient design of parallel systems

Application studies in the areas of image- and video-processing indicate th at between 50%-80% of the power cost in these systems is due to data storag e and transfers. This is especially true for multiprocessor realizations be cause conventional parallelization methods ignore the power cost and focus only on performance. However, the power consumption also heavily depends on the way a system is parallelized. To reduce this dominant cost, we propose to address the system-level storage organization for the multidimensional signals as a first step in mapping these applications, before the paralleli zation or partitioning decisions (in particular, before the hardware/softwa re (HW/SW) partitioning, which is traditionally done too early in the desig n trajectory). Our methodology is illustrated on a parallel quadtree-struct ured difference pulse-code modulation,ideo codec.