A 1-V, 1-Vp-p input range, four-quadrant analog multiplier using Neuron-MOS transistors

In this paper, a four-quadrant analog multiplier consisting of four neuron- MOS transistors and two load resistors is proposed. The proposed multiplier can be operated at only 1 V. Furthermore, the input range of the multiplie r is equal to 100% of the supply voltage. The theoretical harmonic distorti on caused by mobility degradation and device mismatchs is derived in detail . The performance of the proposed multiplier is characterized through HSPIC E simulations with a standard 2.0 mu m CMOS process with a double-poly laye r. Simulations of the proposed multiplier demonstrate that the linearity er ror of 0.77% and a total harmonic distortion of 0.62% are obtained with ful l-scale input conditions. The maximum power consumption and -3 dB bandwidth ase 9.56 mu W and 107 MHz, respectively The active area of the proposed mu ltiplier is 210 mu m x 140 mu m.