Neuron-MOS current mirror circuit and its application to multi-valued logic

Citation
J. Shen et al., Neuron-MOS current mirror circuit and its application to multi-valued logic, IEICE T INF, E82D(5), 1999, pp. 940-948
Citations number
10
Categorie Soggetti
Information Tecnology & Communication Systems
Journal title
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
ISSN journal
09168532 → ACNP
Volume
E82D
Issue
5
Year of publication
1999
Pages
940 - 948
Database
ISI
SICI code
0916-8532(199905)E82D:5<940:NCMCAI>2.0.ZU;2-V
Abstract
A neuron-MOS transistor (nu MOS) is applied to current-mode multi-valued lo gic (MVL) circuits. First, a novel low-voltage and low-power nu MOS current mirror is presented. Then, a threshold detector and a quaternary T-gate us ing the proposed nu MOS current mirrors are proposed. The minimum output vo ltage of the nu MOS current mirror is decreased by VT (threshold voltage), compared with the conventional double cascode current mirror. The nu MOS th reshold detector is built on a nu MOS current comparator originally compose d of nu MOS current mirrors. It has a high output swing and sharp transfer characteristics. The gradient of the proposed comparator output in the tran sfer region can be increased 6.3-fold compared with that in the conventiona l comparator. Along with improved operation of the novel current comparator , the discriminative ability of the proposed nu MOS threshold detector is a lso increased. The performances of the proposed circuits are validated by H SPICE with Motorola 1.5 mu m CMOS device parameters. Furthermore, the opera tion of a nu MOS current mirror is also confirmed through experiments on te st chips fabricated by VDEC*. The active area of the proposed nu MOS curren t mirror is 63 mu m x 51 mu m.