A capacitive pressure sensor has been implemented by the industrial standar
d 0.8 mu m CMOS (Complementary metal oxide semiconductor) process. The devi
ce layout follows the entire set of CMOS IC (Integrated circuit) design rul
es. The sensing capacitor of the capacitive pressure sensor is composed of
the upper metal (metal 2) and the polysilicon layer. The lower metal layer
(metal 1) serves as the sacrificial layer. After completing the standard CM
OS process, three CMOS-compatible post-processing steps were applied. First
, phosphoric acid was used to etch the sacrificial layer to release the mem
brane of the capacitive pressure sensor. Second, PFCVD (Plasma enhanced che
mical vapor deposition) nitride was utilized to seal all access holes. Fina
lly, RIE (Reaction ion etching) was used to remove nitride on the membrane.
The dimensions of the capacitive pressure sensor are 1.0 mm X 0.9 mm. This
pressure sensor operates linearly in the range of 0 similar to 200kPa, and
the sensitivity is 0.07 mV/kPa.