Development of FeRAM circuit technologies

This paper describes our circuit technologies that can be used to obtain fa st and large-capacity FeRAMs with high reliability. The Non-driven Cell Pla te Line Write/Read Scheme (NDP Scheme) offers a fast access time equivalent to that of DRAMs. This scheme makes it possible to access memory cells wit hout having to drive the highly capacitive cell plate line, thus reducing w rite/read delay time. The Self-Reference Read Scheme is used to produce hig hly reliable FeRAMs, because it avoids the read voltage fluctuation, due to fatigue, imprint, and insufficient retention in the ferroelectric capacito rs, between an accessed memory cell and the corresponding dummy memory cell . These technologies are essential for mega-bit-class FeRAMs.