SELECTIVE VICTIM CACHING - A METHOD TO IMPROVE THE PERFORMANCE OF DIRECT-MAPPED CACHES

Although direct-mapped caches suffer from higher miss ratios as compar ed to set-associative caches, they are attractive for today's high-spe ed pipelined processors that require very low access times. Victim cac hing was proposed by Jouppi [1] as an approach to improve the miss rat e of direct-mapped caches without affecting their access time. This ap proach augments the direct-mapped main cache with a small fully-associ ate cache, called victim cache, that stores cache blocks evicted from the main cache as a result of replacements. We propose and evaluate an improvement of this scheme, called selective victim caching. In this scheme, incoming blocks into the first-level cache are placed selectiv ely in the main cache or a small victim cache by the use of a predicti on scheme based on their past history of use. In addition, interchange s of blocks between the main cache and the victim cache are also perfo rmed selectively. We show that the scheme results in significant impro vements in miss rate as well as the average memory access time, for bo th small and large caches (4 Kbytes-128 Kbytes). For example, simulati ons with ten instruction traces from the SPEC '92 benchmark suite show ed an average improvement of approximately 21 percent in miss rate ove r simple victim caching for a 16-Kbyte cache with a block size of 32 b ytes; the number of blocks interchanged between the main and victim ca ches reduced by approximately 70 percent. Implementation alternatives for the scheme in an on-chip processor cache are also described.