CSP compatibility in the SMT assembly process

To achieve integration of chip scale package (CSP) devices into main stream surface mount technology (SMT) assembly, various experiments have been req uired. In process development, experiences learned from flip chip attach an d ball grid array (BGA) assembly were utilized. Key process parameters for CSP assembly were defined and some of those key factors were optimized. The y will be presented in this paper. Some observations during prototype build have been documented for correlation with reliability results in the futur e. The requirements for further CSP assembly studies will also be addressed in this paper.