A 13-bit, 2.2-MS/s, 55-mW multibit cascade Sigma Delta modulator in CMOS 0.7-mu m single-poly technology

This paper presents a CMOS 0.7-mu m Sigma Delta modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16, It uses fully differential switched-capacitor circuits with a clock frequency of 35 .2 MHz, and has a power consumption of 55 mW, Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth-order shaping function has been realiz ed using a cascade architecture with three stages; the first stage is a sec ond order modulator, while the others are first-order modulators-referred t o as a 2-1-1(mb) architecture. The quantizer of the last stage is 3 bits, w hile the other quantizers are single bit. The modulator architecture and co efficients ha ce been optimized for reduced sensitivity to the errors in th e 3-bit quantization process. Specifically, the 3-bit digital-to-analog con verter tolerates 2.8% FS nonlinearity without significant degradation of th e modulator performance, This makes the use of digital calibration unnecess ary, which is a keg point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the propos ed modulator obtains a larger signal-to-noise-plus-distortion ratio than pr evious multibit cascade architectures. On the other hand, as compared to a 2-1-1(single-bit) modulator previously designed for a mixed-signal asymmetr ical digital subscriber line modem in the same technology [1], the modulato r in this paper obtains one more bit resolution, enhances the operating fre quency by a factor of two, and reduces the power consumption by a factor of four.