A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LAN'S and WAN's

A 2,5-Gb/s monolithic clock and data recovery (CDR) IC using the phase-lock ed loop (PLL) technique is fabricated using Si bipolar technology. The outp ut jitter characteristics of the CDR can be controlled by designing the loo p-gain design and by using the switched-filter PLL technique, The CDR IC ca n be used in local area networks (LAN's) and in long-haul backbone networks or wide-area networks (WAN's). Its power consumption is only 0.4 W, For LA N's, the jitter generation of the CDR when the loop gain is optimized is 1. 2 ps (0.003 UI), The jitter characteristics of the CDR optimized for WAN's meet all three types of STM-16 jitter specifications given in ITU-T Recomme ndation G.958. This is the first report on a CDR that can be used for both LAN's and WAN's. This paper also describes the design method of the jitter characteristics of the CDR for LAN's and WAN's.