Multiple twisted dataline techniques for multigigabit DRAM's

To provide reliable scaled DRAM's, new multiple twisted dateline techniques are proposed and analyzed. Their effectiveness in reducing both the bitlin e (BL) and wordline (WL) coupling noises in scaled DRAM's was evaluated by means of soft-error-rate measurements on 256-Mbit and 1-Gbit DRAM test chip s. At the 1-Gbit level of integration, in our proposed scheme-compared to t he conventional twisted bitline (TBL) scheme-the chip area penalty due to t wisting is reduced by 66% and the BL coupling noise is reduced by 45%. At t he 256-Mbit level, when the proposed technique is applied to both the BL an d WL structures, me achieved a 64% coupling noise reduction compared to the conventional TBL and WL schemes. Faster data access time can also be expec ted when the proposed technique is applied to BL and/or WL structures.