A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems

In this paper, we describe an energy-efficient carry-lookahead adder using reversible energy recovery logic (RERL), which is a new dual-rail reversibl e adiabatic logic. We also describe an eight-phase, clocked power generator that requires an off chip inductor, For the energy-efficient design of rev ersible logic, we explain how to control the overhead of reversibility with a self-energy-recovery circuit. A test chip was implemented with a 0.8-mu m CMOS technology, which included two 16-bit carry-lookahead adders to allo w fair comparison: an RERL one and a static CMOS one. Experimental results showed that the RERL adder had substantial advantages in energy consumption over the static CMOS one at low operating frequencies. We also confirmed t hat we could minimize the energy consumption in the RERL circuit by reducin g the operating frequency until adiabatic and leakage losses were equal.