From design validation to hardware testing: A unified approach

In this paper we propose a new approach that addresses both the problems of design validation and hardware testing since the early stages of the desig n flow. The approach consists in adapting the mutation testing, a software method, to circuits described in VHDL. At the functional level, the approac h behaves as a design validation method and at the hardware level as a clas sical ATPG. Standard software test metrics are used for assessing the quali ty of the design validation process, and the hardware fault coverage for as sessing the test quality at the hardware level. An enhancement process that allows design validation to be efficiently reused for hardware testing is detailed. The approach is shown to be efficient upon a set of representativ e circuits.