Exploiting behavioral information in gate-level ATPG

Citation
S. Chiusano et al., Exploiting behavioral information in gate-level ATPG, J ELEC TEST, 14(1-2), 1999, pp. 141-148
Citations number
10
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS
ISSN journal
09238174 → ACNP
Volume
14
Issue
1-2
Year of publication
1999
Pages
141 - 148
Database
ISI
SICI code
0923-8174(199902)14:1-2<141:EBIIGA>2.0.ZU;2-H
Abstract
This paper aims at broadening the scope of hierarchical ATPG to the behavio ral-level. The main problem is identified, namely the mismatch of timing mo dels between the behavioral- and gate-levels. As a main contribution of thi s paper, a theoretical analysis of this problem led to the definition of a novel concept, that of dominated patterns, that captures the needed link be tween the levels. Some metrics are defined, taken from the software realm, that allow generation of test patterns at the behavioral-level. To validate the concept correctness, different ATPG systems are presented, and experim ental results show an improvement in the test quality, thanks to the exploi tation of behavioral-level information.