Low noise CMOS readout for CdZnTe detector arrays

A low noise CMOS readout for CdTe and CdZnTe X- and gamma-ray detector arra ys has been designed and implemented in the CMOS 2 mu m low noise analog pr ocess provided by the multi-chip program of Metal Oxide Semiconductor Imple mentation Service. The readout includes CMOS low noise charge sensitive pre amplifier and a multiplexed semi-Gaussian pulse shaper. Thus, each detector has a dedicated charge sensitive preamplifier that integrates its signal, while a single shaping amplifier shapes the pulses after the multiplexer. L ow noise and low-power operation are achieved by optimizing the input trans istor of the charge sensitive preamplifier. Two optimization criteria are u sed to reduce noise. The first criterion is based on capacitance matching b etween the input transistor and the detector. The second criterion is based on bandwidth optimization, which is obtained by tailoring the shaper param eters to the particular noise mechanisms of the MOS transistor and the CdZn Te detector. Furthermore, the multiplexing function incorporated in the sha per provides low power and reduces chip area. The system is partitioned int o a chip containing the charge amplifiers and a chip containing the semi-Ga ussian pulse shaper and multiplexer. This architecture minimizes coupling f rom multiplexer switches as well as shaper output to the input of the charg e sensitive preamplifiers. (C) 1999 Elsevier Science B.V. All rights reserv ed.