SRAM BITLINE CIRCUITS ON PD SOI - ADVANTAGES AND CONCERNS

Authors
KUANG JB RATANAPHANYARAT S SACCAMANGO MJ HSU LLC FLAKER RC WAGNER LF CHU SFS SHAHIDI GG
Citation
Jb. Kuang et al., SRAM BITLINE CIRCUITS ON PD SOI - ADVANTAGES AND CONCERNS, IEEE journal of solid-state circuits, 32(6), 1997, pp. 837-844
Citations number
10
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE journal of solid-state circuits → ACNP
ISSN journal
00189200
Volume
32
Issue
6
Year of publication
1997
Pages
837 - 844
Database
ISI
SICI code
0018-9200(1997)32:6<837:SBCOPS>2.0.ZU;2-S
Abstract
This paper presents a study of sub-0.25-mu m CMOS SRAM bitline circuit ry on partially depleted (PD) silicon-on-insulator (SOI) technology. S OI implementations outperform conventional bulk ones due to significan t reduction of collective device junction capacitance on the bitlines. Floating body effects are investigated for both read and write cycles , Array content dependent behaviors are identified for the first time and analyzed with worst-case temporal and spatial pattern combinations .