A high-speed analog median circuit is presented using a two-stage arch
itecture to minimize the errors around the transition corners, Prototy
pes have been designed and built using the Orbit 2-mu m CMOS process,
The design has been optimized for low crossover distortion and fast tr
ansient recovery in less than 200 ns, The active area is 0.2 mm(2), an
d the circuit dissipates 7 mW from a single 5 V supply while being abl
e to drive an external 30 pF capacitor.