Clock jitter and quantizer metastability in continuous-time delta-sigma modulators

The performance of continuous-time (CT) delta-sigma modulators (Delta Sigma M's) suffers more severely from time jitter in the quantizer clock than di screte-time designs. Clock jitter adds a random phase modulation to the mod ulator feedback signal, which whitens the quantization noise in the band of interest and hence degrades converter resolution. Even with a perfectly un iform sampling clock, a similar whitening can be caused by metastability in the quantizer: a real quantizer has finite regeneration gain, and thus, qu antizer inputs near zero take longer to resolve. This paper quantifies the performance lost due to clock jitter in a practical integrated CT Delta Sig ma M clocked with an on-chip voltage-controlled oscillator. It also charact erizes metastability in a practical integrated quantizer using the quantize r output zero-crossing time and rise time as a function of both quantizer i nput voltage and the slope of the input voltage at the sampling instant, an d predicts the maximum-achievable performance of a practical CT Delta Sigma M given jitter and metastability constraints.