Morphology and integration of rough polycrystalline silicon films for DRAMstorage cell applications

This study evaluates the important aspects of deposition and integration of rough polycrystalline silicon films for dynamic random access memory (DRAM ) storage capacitor applications. Electrical performance of rough polycryst alline films is investigated in terms of grain morphology and microstructur al control. It is shown that the morphology, roughness, and doping of the f ilms strong ly affect the capacitor electrical performance. A strong correl ation is observed between the surface roughness measured in terms of reflec tance and the electrical area enhancement factor (AEF) of the films. Leakag e current performance of rough and control/smooth electrode devices incorpo rating NO dielectric is evaluated. The results demonstrate that the leakage current density of the devices with rough electrode is less than the AEF t imes the leakage current density of the devices with control polysilicon el ectrode. Various integration approaches to fabricate the rough polysilicon storage electrode are examined. Lower thermal budget processing sequences a re shown to be viable options. Rapid thermal based doping and dopant activa tion anneal processes are demonstrated as alternatives to high temperature furnace annealing sequences. Capacitance-voltage data is presented with AEF and dopant depletion analysis for devices incorporating lower thermal budg et sequences. It is shown that phosphine gas-doping of the rough polysilico n electrode increases the AEF by 17% as a consequence of the doping process . (C) 1999 The Electrochemical Society. S0013-4651(98)08-104-X. All rights reserved.