Static test compaction for synchronous sequential circuits based on vectorrestoration

We propose a new static test compaction procedure for synchronous sequentia l circuits. The procedure belongs to the class of procedures that omit test vectors from a given test sequence in order to reduce its length without r educing the fault coverage. The previous procedure that achieved high level s of compaction using this approach attempted to omit test,vectors from a g iven test sequence one at a time or in subsequences of consecutive vectors. The omission of each vector or subsequence required extensive simulation t o determine the effects of each omission on the fault coverage. The procedu re proposed here first omits (almost) all the test vectors from the sequenc e, and then restores some of them as necessary to achieved the required fau lt coverage. The decision to restore a vector requires simulation of a sing le fault. Thus, the overall computational effort of this procedure is relat ively low. The loss of compaction compared to the scheme that omits the vec tors one at a time or in subsequences is small in most cases. Techniques to speed-up the restoration process are also investigated;, including conside ration of several faults in parallel during restoration, and the use of a p arallel fault simulator. Experimental results are presented to demonstrate the effectiveness of vector restoration as a static compaction technique.