The GRD chip: Genetic reconfiguration of DSPs for neural network processing

This paper describes the GRD (Genetic Reconfiguration of DSPs) chip, which is evolvable hardware designed for neural network applications. The GRD chi p is a building block for the configuration of a scalable neural network ha rdware system. Both the topology and the hidden layer node functions of a n eural network mapped on the GRD chips are dynamically reconfigured using a genetic algorithm (GA). Thus, the most desirable network topology and choic e of node functions (e.g., Gaussian or sigmoid function) for a given applic ation can be determined adaptively. This approach is particularly suited to applications requiring the ability to cope with time-varying problems and real-time constraints. The GRD chip consists of a 100Mhz 32-bit RISC proces sor and 15 33Mhz 16-bit DSPs connected in a binary-tree network. The RISC p rocessor is the NEC V830 which executes mainly the GA. According to chromos omes obtained by the GA, DSP functions and the interconnection among them a re dynamically reconfigured. The GRD chip does not need a host machine for this reconfiguration. This is desirable for embedded systems in practical i ndustrial applications. Simulation results on chaotic time series predictio n are two orders of magnitude faster than on a Sun Ultra 2.