CMOS and Memories: From 100 nm to 10 nm!

The dimensional limit where field-effect can still be gainfully employed is of the order of 10 nm. Other constraints that limit our use of field-effec t are: random fluctuations in doping and thickness, gate insulator tunnelin g, electrostatic control of the channel, resistive and capacitive parasitic s, device leakage and reliability, and the economics of any solution propos ed. This contribution shows that physics allows devices that fulfill the ne ed of microelectronics down to 10 nm length scale and summarizes experiment al results that point out some of the directions that might be appropriate.