Technology for nanoelectronic devices based on ultra-high vacuum scanning tunneling microscopy on the Si(100) surface

We describe two process steps in an STM-based fabrication technology for na noelectronic devices. First, we have fabricated Co/Si metal lines on Si(100 ) surfaces by UHV-STM based nanolithography on a monohydride passivation la yer. The STM tip was used to define depassivated lines (<10 nm in width) by electron-stimulated H desorption followed by Co deposition at submonolayer coverage. The resulting Co/Si wires show a granular structure with tough b oundaries, but after anneal at 410 degrees C this changes into a compact st ructure possibly due to strong silicidation. Second, fabrication and analys is of tungsten contact metallization that will allow electrical transport s tudies along these metallic nanostructures has been performed.