Improved post etch cleaning for low-k and copper integration for 0.18 mu mtechnology

A key challenge for 0.18 mu m technology is the interconnect RC delay, whic h is the limiting factor for device performance. This delay can be reduced by the use of a low-k dielectric and copper. Some of the difficulties of in tegrating these interconnects sue discussed, and a new strategy for post di electric etch cleaning is presented.